This invention relates to a first-in-first-out register device for use in an information processing device to successively memorize a queue of instructions.
A conventional information processing device of the type described comprises an address calculation circuit for calculating an address from each instruction and an execution circuit for carrying out an operation indicated by an instruction. At any rate, both the address calculation circuit and the execution circuit execute instructions under the control of a pipeline controller in pipeline fashions different from each other. In this event, a first-in-first-out register device is located between the address calculation circuit and the execution circuit, to memorize the instructions in the form of a queue between the address calculation circuit and the execution circuit.
Herein, it is assumed that the address calculation circuit often accesses a bus when it executes a specific instruction, such as a read instruction, a write instruction, so as to read or write a data signal from or into a memory connected to the address calculation circuit through the bus. The data signal is memorized in a data register before it is processed by the execution circuit. Such a bus access operation lasts for a bus cycle or an execution time which is defined by a single clock cycle or a plurality of clock cycles.
It is to be noted that the bus cycle may be variable from one to another in such an information processing unit. In this case, when the bus cycle becomes short, the data signal may be read out of the memory before the specific instruction for the data signal is read out of the first-in-first-out register device and executed by the execution circuit. Under the circumstances, the data signal might be extinct, or erased from the data register, prior to execution of the specific instruction.